Delay locked loops (DLLs) are used to align data output from circuits, such as memory circuits, to the clock signal of a host. A DLL receives a clock signal from a host and delays the clock signal to provide an output signal to an off-chip driver (OCD) to align data output by the OCD to the clock signal. The DLL compensates for differences in timing between the circuit and the host. Typically, a DLL includes a delay line, a feedback delay, and a phase detector. The delay line delays the clock signal to provide the output signal. The output signal is provided to the feedback delay. The feedback delay delays the output signal to provide a feedback signal to the phase detector. The feedback delay compensates for the differences in timing between the circuit and the host. The phase detector compares the feedback signal to the clock signal and outputs a control signal to adjust the delay of the delay line to reduce the phase difference between the clock signal and the feedback signal to zero.
One type of DLL uses a synchronous mirror delay (SMD). A SMD typically includes an enable input, a signal input, and a signal output. With the enable signal at a logic high, a rising edge of the input signal is mirrored with respect to the falling edge of the enable signal. The rising edge of the output signal is delayed with respect to the falling edge of the enable signal by a time equal to the delay between the rising edge of the input signal and the falling edge of the enable signal. A SMD can also mirror a falling edge of the input signal with respect to a rising edge of the enable signal.
A DLL based on a SMD has a number of limitations. One limitation is that the DLL is limited to a maximum frequency by the feedback delay. The feedback delay for the DLL cannot be greater than the cycle time of the clock signal; otherwise the delay between the rising edge of the input signal and the falling edge of the enable single is negative. To overcome this limitation, typically the clock signal is divided by two, four, eight, or other suitable number so that the feedback delay is less than the cycle time of the divided clock signal. This method, however, increases the number of SMD lines to two times the divisor of the clock signal. For example, if the clock signal is divided by four, eight SMD lines are needed to build the DLL. Increasing the number of SMDs increases the cost of the DLL. Another limitation of a DLL using a SMD is that if a rising edge to be mirrored falls too close to the rising or falling edge of the clock signal, the SMD may perform poorly in mirroring the signal.